CMOS: Design Considerations in Monolithic Circuits 4.5 The circuit of Fig. P4.5 is the CMOS counterpart...

V_ovn = squareroot 2 times I_D/k_n = squareroot 2 times 0.2/0.4 = 1.0V, V_op = squareroot 2 times 0.2/0.175 1.5 V V_0 (max) = V_DD - V_ovp = 5 - 1.5 = 3.5 V: V_0 (min) = V_sn + V_ovn = -V_asn + V_ovn = -(V_tn + V_ov) + V_ovn = -V_tn = -1.0V Mid range value is V_0 = 1/2 [V_0 (max) + V_0 (min)] = 1/2 [3.5 - 1] = 1.25 V b) Imposing I_Dn = I_Dp = 200 mu A @ V_0 = 1.25 gives 200 = 400/2 (V_as^-1)^2 (1 + V_Dsn/V_An) = 200(V_as^-1)^2 (1 + 1.25 - (-1/as)/25) = > V_as = 1.942 V 200 = 400/2 (V_sa - 0.75)^2 (1 + V_sDp/V_Ap) = 87.5 (V_sa - 0.75)^2 (1 + 5 - 1.25/20) = > V_sa = 2.137 V c) r_on = V_An/I_Dn = 25/0.2 = 125 k Ohm: r_op = 20/0.2 = 100 k Ohm g_mn = squareroot 2 k_n I_D = squareroot 2 times