## Question

###### Single bus archicture Below are the functional forms of instructions we'd like to implement in the...

single bus archicture

Below are the functional forms of instructions we'd like to implement in the multi-cycle datapath. Find the number of cycles each of these instructions would take to execute. Instruction #1 Reg(rs) - Immediate -> Reg(rt) This instruction takes cycles. Instruction #2 Mem[Reg(rs)+Regírt)) -> PC This instruction takes cycles Instruction #3 Mem Mem [ Regirs) ]] + Regírt) -> Regird) This instruction takes cycles.

## Answers

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Step 1 Let us forst discuss about addressing modes

② Immediate Addressing mode : This mode is used to access the constant. In this mode data present in the address field of Instruction. I'S си 8-bit opcode Addr. Just I Data Data Address field value③ Ou Register AM!- - This mode is used to access the local variables. this mode, data is present in the registers, the corresponding register name will be maintained im address field of an inostruction as effective addiers. a Justu Design Opcode | Addr. EA {reg name} Reg. file 82 Data --- Data accers To6 Direct AM - (Absolute AM) This mode is used to access the static variable. In this mode , clata is present in the memory, The corresponding memory address will be maintained in the address field o of an instruction as effective address, asust Design opcode Addr. Y EA mern. Addr} memory 0000 Data scata access. 2006 FFFF* Memory Tudirect AM - - In this mode effective address is present in the memory corresponding memory address will be maintained in address field of address of the effective address. the the an Instruction a Insth! op code Adder. •EA's [Addr. field value] Data . Mem. CEAJ - [[mem Adond] OOOO • Achiory: →2000 Data (20) Data Access. Access I MR To access En IMR To access Data. 4000 EA (2000) EA FFFFStep2 - let I'MR takes touche IRR takes laucle JALU takes tcycle MR Memory Reference RR Register Reference AL Arithmetic Logic unit Step Insthi Regers) - Immediate - Regcit) [opcode / Addr Data Insth cycle FC CFetch cycle) EC CExecution cycle ) of PD WB IF ID IMR IMR TRR It-Insth fetch ID - Insth Decode of opesard Fetch PD Process Data WB Write Back -Multi-cycle Phases Insth I takes 2MRTIRR = 2 cycle + taycle = 3cycleStep3 Ingth 2 mem[ Reg Crs) + Regcrt)] +PC9 ideia IRR un ( IRR A LAR LALU IMR FC IF ID 10012 Ecob D OF PD WB712 si Soberand? JRR RR Y LAW TAR IMR IMR IMR Insth 2 takes 3MR +3RR HZALU Staciju = 7cycle Stepy Insth 3 m I mempRegers)] + RegCits » Regard) IRR IRR TRR IMR IMR TALL EX FC IF ID PD WB OF S2 IMR IMR IRR IRR LAL 1 IRR 2MR Inst" 3 takes UMR + 3RR TLALU = 8cycle

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